Vertical power delivery enables cutting-edge processing
New developments are challenging power system designers with managing PDN impedance voltage drops, transient performance specifications and power loss
Dedicated factorized power solutions for computing
Dedicated factorized power solutions for computing
The Data Center PRM & VTM solutions leverage the value of Factorized Power Architecture™ in demanding, non-isolated server applications providing 48V Direct to POL power conversion for CPU, GPU, ASIC, and memory loads. These solutions provide high density, high efficiency, and low noise conversion for high performance computing.
Features and Benefits
PRM features and benefits
Non-isolated, regulator
ZVS buck-boost topology
~1MHz switching frequency
Power density up to 1,700W/in3 (103W/cm3)
Features and Benefits
VTM features and benefits
Non-isolated, voltage transformer
Up to 135A
High-frequency Sine Amplitude Converter™
Fast transient response
Select a PRM
0 Products
| Input Range (V) | Type | Output Range (V) | Power | Package | Add to cart / view details | ||
|---|---|---|---|---|---|---|---|
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Input Range (V): 38 – 60 | Type: VTM Compatible PRM | Output Range (V): 38 – 50 | Power: 240 | Package: 10 x 14 x 2.5 mm (LGA SiP) | View details | |
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Input Range (V): 38 – 60 | Type: VTM Compatible PRM | Output Range (V): 28 – 60 | Power: 200 | Package: 10 x 10 x 2.5 mm (LGA SiP) | View details | |
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Input Range (V): 38 – 60 | Type: VTM Compatible PRM | Output Range (V): 28 – 54 | Power: 100 | Package: 10 x 10 x 2.5 mm (LGA SiP) | View details | |
Select a VTM
0 Products
| Vin (V) | Vout (V) | Output Current (A) | Package | Add to cart / view details | ||
|---|---|---|---|---|---|---|
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Vin (V): 48 (0 - 55) | Vout (V): 2.0 (0 - 2.3) | Output Current (A): 88 | Package: 1323 ChiP | View details | |
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Vin (V): 48 (0 - 60) | Vout (V): 1.0 (0 - 1.25) | Output Current (A): 107 | Package: 1323 ChiP | View details | |
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Vin (V): 48 (0 - 55) | Vout (V): 2.0 (0 - 2.3) | Output Current (A): 95 | Package: 1323 ChiP | View details | |
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Vin (V): 40 (0 - 60) | Vout (V): 1.0 (0 - 1.5) | Output Current (A): 130 | Package: 1323 ChiP | View details | |
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Vin (V): 48 (0 - 60) | Vout (V): 1.0 (0 - 1.25) | Output Current (A): 135 | Package: 1323 ChiP | View details | |
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Vin (V): 48 (0 - 52) | Vout (V): 1.2 (0 - 1.63) | Output Current (A): 76 | Package: 0823 ChiP | View details | |
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Vin (V): 48 (0 - 60) | Vout (V): 1.2 (0 - 1.25) | Output Current (A): 105 | Package: 0823 ChiP | View details | |
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Resources
Resources for the design engineer
New Vicor innovations unleash xPU performance at OCP China Day 2022
Current multiplier technology advances enable new AI processor power solutions
PCB layout and thermal design for high-density modular power systems
High-density loads like processors for artificial intelligence & supercomputing have become sophisticated & fast, pushing power components to capacity
Where fixed-ratio converters fit in high-power delivery systems
The density and efficiency of a fixed-ratio converter plays a critical role in enabling PDN architecture to deliver high performance
- AN:005 – FPA Printed Circuit Board Layout Guidelines
- AN:017 – RoHS-Compliant Through-Hole VI Chip Soldering Recommendations
- AN:031 – Through-Hole ChiP Package Soldering Guidelines
- AN:032 – Designing High Power Parallel Arrays with PRMs
- AN:033 – Fault Management Circuit
- AN:034 – Creating Higher Voltage Outputs using Series Connected Sine Amplitude Converters
- UG:013 – VI Chip Configurable PRM® Module Evaluation Board Users Guide
- UG:014 - VI Chip VTM® Evaluation Board User Guide
- UG:016 – VI Chip PRM®Remote Sense Evaluation Board User Guide
- For use with PCB part numbers 38693 and 39573
- Datacenter Power Delivery Architectures: Efficency and Annual Operating Costs
- 48 is the New 12 : Server Power in the Rapidly Growing Digital Universe
- FPA Overview: An Introduction to FPA
- Enabling Next Generation High-Density Power Conversion
- High Current, Low Voltage Solution for Microprocessor Applications from 48 V Input
- Efficient Power Conversion Solutions
- Dual-Stage Feedback Technique for Single-Pole Feedback Compensation
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